1. Field of the Invention
The present invention relates to integrated circuit test structures and procedures. More specifically, the present invention relates to a test structure and testing procedure for silicided junctions of devices isolated using shallow trench and refill techniques.
2. Description of the Related Art
Shallow trench and refill techniques have been developed to effectively isolate devices in deep-submicron MOS technologies. A shallow trench and refill isolation structure is formed by etching a relatively shallow trench, for example 0.3-0.5 .mu.m in depth, into a silicon substrate, growing a thin thermal oxidation layer on the trench walls to control silicon-silicon oxide interface quality, and refilling the trench with an insulator material. The surface is then planarized after refill to form an isolation structure.
Shallow trench and refill techniques advantageously form a small isolation spacing due to elimination of bird's beak and reduction of channel-stop dopant redistribution. The fully-recessed form of the resulting isolation structure makes possible a desirable planar surface. In addition, field-oxide thinning in narrow isolation spaces is avoided so that threshold voltage is maintained at a constant level as a function of channel width. A further advantage of shallow trench and refill techniques is that MOSFETs fabricated with fully-recessed oxide isolation exhibit a relatively large transconductance g.sub.m values. Also, fully-recessed structures with sharp lower corners furnish improved isolation efficiency due to a "corner effect" in which field lines at the bottom corners of a trench spread in the vicinity of a corner, leading to a higher threshold at the corners.
However, several limitations and disadvantages are characteristic of shallow trench and refill techniques.
One drawback of the isolation structure formed by the shallow trench and refill technique is a possible degradation in device operating behavior. In a conventional LOCOS-isolated MOSFET such as a MOSFET 100 shown in FIG. 1, a polysilicon gate formed across the surface of a device slopes away from the device beginning at the edge of the isolation oxide region. In the case of a MOSFET isolated using local oxidation of silicon (LOCOS) isolation, for example MOSFET 200 shown in FIG. 2A and a MOSFET isolated using a shallow trench isolation, for example MOSFET 202 shown in FIG. 2B, the gate region forms a flat surface across the isolation so that the part of the gate overlying the field region creates a larger two-dimensional fringing field on the corner and sidewall of the silicon mesa structure as compared to the behavior of a LOCOS-isolated MOSFET. This two-dimensional fringing field establishes a corner parasitic MOSFET in parallel with the main channel device. The parasitic device is activated at gate voltages lower than the voltages that activate the main channel device, increasing the subthreshold leakage of the device. This parasitic effect is enhanced if the isolation oxide region is partly etched below the silicon mesa top surface, causing to wrap around the corner of the mesa structure. The regions of the channel near the edges of the device behave much differently then the region at the center of the mesa.
Subthreshold characteristics of narrow MOSFETs which are isolated by refilled shallow trench structures are sensitive to the shape of the upper trench corner. Edges of a silicon mesa at upper corners of a shallow trench structure device are activated by the portion of the gate that overlaps such corner regions. Edge activation becomes even stronger when the isolation region is partially eroded so that the gate wraps around the corner of the device.
Accordingly, shallow trench isolation is best achieved by a gate structure that runs flat across the isolation region, which is attained when the device structure prior to polysilicon layer is planar. One fabrication technique for achieving a planar device structure is a process utilizing reactive ion etching (RIE) etchback followed by a chemical-mechanical polishing operation.
Another drawback is thinning of the gate oxide at the edge of the trench. Thinned gate oxide degrades gate oxide reliability and worsens the parasitic device problem since a thinner gate oxide increases the electric field strength at the trench corner.
The corner is also exposed from spacer etch and other oxide etches, both wet and dry etches, after formation of the shallow trench isolation.
Another problem with shallow trench isolation arises with the usage of salicide processing. Salicide processing is used to reduce resistance values that result from reduction in the contact dimensions of integrated circuits causing increases in contact resistance and sheet resistivity of shallow-junctions of source/drain regions. Referring to FIG. 3, a sectional view of a semiconductor wafer 300 shows a device area 312 formed in a silicon substrate 310 and including an N+ type doped area 314 and a P- type doped area 316. Isolation oxide 318 is formed lateral to the device area 312. During salicide processing, a layer of silicide material 320 is formed covering the device area 312. The silicide material 320 may wrap around a corner 322 of the silicon device area 312, forming a silicide layer 324 at a level below the area covering the surface 326 of the silicon device area 312. The unintended silicide layer 324 can cause junction leakage by formation of silicide in too close a proximity to the junction 328 of the N+ type 314 and P- type 316 doped areas. In some instances, the junction 328 may be short-circuited. Subsequent processing, including etching and cleaning processes, erodes the silicon even further, approaching or extending to the junction, causing junction leakage and potentially leading to a short-circuit condition.
To fabricate operational integrated circuits, junction leakage and short-circuiting must be prevented. However, many various semiconductor processing steps other than silicide formation at the junctions may also cause junction leakage and short-circuiting.
What is needed is a test structure that accurately determines whether salicide processing and silicide formation in close proximity to device junctions is a cause of junction leakage and short-circuiting.